circuit note cn-0121 circuit designs using analog devices products apply these product pairings quickly and with confidence. for more information and/or support call 1 -800- analogd (1 -800-262-5643) or visit www.analog.com/circuit . devices connected /referenced AD9910 1 gsps direct digital synthesizer (dds) ad9520 clock generator and distribution ic adclk846 high speed lvds clock fanout buffer synchronizing multiple AD9910 1 gsps direct digital synthesizers rev. a circuits from the lab from analog devices have been designed and buil t by analog devices engineers. standard engineering practices have been employed in the design and construction of each circuit, and their function and performance ha ve been tested and verified in a lab environment at room temperature. however, you are solely responsible for testing the circuit and determining its suitability and applicability for your use and application. accordingly, in no event shall analog devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any circuit from the lab . (continued on last page) one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u .s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2009 analog devices, inc. all rights reserved. circuit function and benefits synchronization of multiple dds devices allows precise digital tuning control of the phase and amplitude across multiple frequency carriers. this type of control is useful in radar appli cations and quadrature (i/q) up conversio n for side - band suppression. the circuit in figure 1 demonstrate s how to synchronize four AD9910 1 gsps, dds chips using t he ad9520 clock generator and the adclk846 clock fanout buffer . the result is precise phase alignment betwee n the clock and output signals of four AD9910 devices . AD9910 (master) + sync_in C sync_in C sync_out sync_clk aout clk1 clk1 clock cmos levels cmos level pecl levels ref clk io_upd a te AD9910 (slave) ref clk + sync_in C sync_in + sync_in C sync_in + sync_in C sync_in sync_clk aout io_upd a te AD9910 (slave) ref clk sync_clk aout io_upd a te AD9910 (slave) ref clk sync_clk aout io_upd a te + sync_out scope ch1 ch2 ch3 ch4 dg2020a data generator ad9520 q0 q1 q2 q3 q4 adclk846 q0 q0 q1 q1 q2 q2 q3 q3 l vds levels l vds levels 08514-001 figure 1. setup for synchronization of multiple AD9910 s (simplified schematic: decoupling, power, and all connections not shown)
cn-0121 circuit note rev. a | page 2 of 3 circuit description the circuit in figure 1 was constructed by connecting the respective evaluation boards for the individual products. connections were made with matched cable lengths. the first of three basic requirement s to synchronize multiple AD9910 s is to provi de a co - incident reference clock ( ref cl k). the setup uses the ad9520 as the ref clk source for each AD9910 dds . the ad9 520 runs off a n external crystal and the internal pll. the ad9520 distributes phase aligned 1 ghz ref clks (pecl outputs) to all four a d99 10 evaluation boards . it also provides a cmos output clock to the tektronix dg2020a data pattern generator for the io_update. the next step for synchronization is to align the rising edge of sync_clk for all four AD9910 s. the sync_clk provi des the refe rence for a co - incident io_update. sync_clk alignment is accomplished using the internal synchronization capability of the AD9910 . the adclk846 distributes phase aligned sync_ins to all four AD9910s. see the AD9910 data sheet for more details on synchroniz ation capability . figure 2 shows all four sync_clks with the AD9910 internal synchronization circuit dis abled. note that the sync_clks are not inherently aligned even when the ref clks are phase aligned. to phase align the sync_clk rising edges, one AD9910 is programmed as the master device and the others as slave devices. the sync_out of the master device is an lvds signal buffered and distributed by the adclk846 to all AD9910 evaluation boards. the sync_in signal (lvds) must meet internal setup and hold time requirements of each devices system clock. to help support this timing requirement, the AD9910 features the ability to delay the sync_out of the master. for further flexibility, the internal sync_in path of each device can be independently delayed. 08514-002 ch1 1.00v ? ch2 1.00v ? ch3 1.00v ? ch4 1.00v ? m2.00ns ch2 480mv 1 2 3 4 c3 frequenc y 250.76mhz low signa l amplitude figure 2. sync_clks are not aligned . in the setup of figure 1, connections between boards were made using matched cables, ma king it possible to use the internal default delay values to phase align the sync_clks. figure 3 shows sync_clk phase alignment via the using the synchronization procedure described. t he last requirement to synchronize multiple dds devices is a co - incident io_up d ate . the io_update must meet setup and hold times to sync_clk. the io_update shown in figure 1 is sent synchronous ly to the sync_clk. the last requirement now enables the dds outputs to be controlled. figures 4 and 5 show the dds outputs in phase alignment. having the devices synchronized to one another now enables predictable phase and/ or amplitude adjustment between ddss. note, in figure 5 the system clock was reduce d to 100 mhz operation , and the outputs were unfiltered to display each dds raw output . figure 5 also shows the value of synchronization wi th each device outputting the same signal. 08514-003 ch1 1.00v ? ch2 1.00v ? ch3 1.00v ? ch4 1.00v ? m2.00ns ch1 480mv 1 2 3 4 c3 frequenc y 249.54mhz low signa l amplitude figure 3 . sync_clk are aligned. 08514-004 ch2 200mv ? b w ch3 200mv ? b w ch1 200mv ? b w ch4 200mv ? b w m5.00ns ch2 C80v 1 2 3 4 c3 frequenc y 125.321mhz figure 4. filtered dds outputs phase aligned using the setup in figure 1.
circuit note cn-0121 rev. a | page 3 of 3 08514-005 ch1 200mv ? ch3 200mv ? ch4 200mv ? ch2 200mv ? m20.0ns ch2 C80v 1 2 3 4 figure 5. dds unfil tered outputs phase aligned using the setup in figure 1. c ommon variations anal og devices offers a variety of direct digital synthesizer s, c lock distribution chips , and clock b uffers to build a dds - based clock generator. refer to www.analog.com/dds and www.analog.com/clock for more information. learn more an - 823 application note, direct digital synthesizers in clocking applications . analog devices. an - 837 application note, dds - based clock jitter pe rformance vs. dac reconstruction filter performance . analog devices. kester, walt. 2005. the data conversion handbook . analog devices. chapters 6 and 7. kester, walt. 2006. high speed system applications . analog devices. chapter 2, optimizing data converter interfaces. kester, walt. 2006. high speed system applications . analog devices. chapter 3, dacs, ddss, plls, and clock distribution. mt - 031 tutorial, grounding data converters and solving the mystery of agnd and dgnd. analog devices. mt - 085 tutorial, fundamentals of direct digital synthesis (dds) , analog devices. mt - 086 tutorial, fundamentals of phase locked loops (pll) , analog devices. mt - 101 tutorial, decoupling techniques . analog devices. data sheets and evaluation boards AD9910 data sheet. AD9910 evaluation board. ad9520 data sheet. ad9520 evaluation board. adclk846 data sheet. adclk846 ev aluation board. revision history 12/09 rev. 0 to rev. a changes to figure 1 .......................................................................... 1 10/09 revision 0: initial version (continued from first page) "circuits from the lab" are intended only for use with analog devices products and are the intellectual property o f analog devices or its licensors. while you may use the "circuits from the lab" in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectual property by application or use of the "circuits from the lab". information furnished by analog devices is believed to be accurate and reliable. however, "circuits from the l ab" are supplied "as is" and without warranties of any kind, express, implied, or statutory including, but not limited to, any impl ied warranty of merchantability, noninfringement or fitness for a particular purpose and no responsibility is assumed by analog devices for their use, nor for any infringements of patents or other rights of third parties that may result from t heir use. ana log devices reserves the right to change any "circuits from the lab" at any time without notice, but is under no obligation to do so. trademarks and registered trademarks are the p roperty of their respective owners. ? 2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. cn08514 -0- 12/09(a)
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